1. Field of the Invention
Embodiments of the present invention relate generally to memory access operations and, more specifically, to a surface resource view hash for coherent cache operations in texture processing hardware.
2. Description of the Related Art
A modern graphics processing unit (GPU) includes texture processing hardware configured to perform a variety of texture-related operations, including texture load operations and texture cache operations. The texture processing hardware accesses surface texture information from the texture cache while rendering object surfaces in a three-dimensional (3D) graphics scene for display on a display device. Surface texture information includes texture elements (texels) used to texture or shade object surfaces in a 3D graphics scene.
The texture processing hardware typically accesses surface texture information using “tuples” rather than via a linear virtual or physical memory address, where a tuple is an ordered list of elements. For example, the texture processing hardware could access a surface texture by specifying a tuple that includes x, y, and z coordinates, an index, and a texture identifier. Accordingly, each cache line resident in the texture cache includes the corresponding memory data, and the tuple representing the first texel location in the cache line.
The texture processing hardware may access surface texture information using multiple views. For example, one view of a 3D texture surface could provide access to the surface texture as a 3D surface where x, y, and z coordinates specify a particular texel in the 3D surface. A second view of the same 3D texture surface could access the surface texture as an array of 2D surfaces, where an index specifies a particular 2D surface, and x and y coordinates specify a particular texel in the 2D surface. A third view of the same 3D texture could access a 2D portion or “slice” of the 3D surface, where x and y coordinates specify a particular texel in the 2D slice.
One drawback with this approach is that such multiple views of a surface may cause cache coherency and consistency problems. If multiple views of a surface texture are simultaneously active, then the texture cache may include multiple texture cache entries that specify the same cache line. Each of the multiple cache entries may specify the tuple corresponding to a different view of the same surface in the texture cache. If the texture processing hardware writes to the cache line corresponding to a first view, then the data may be written to the cache line corresponding to that view. If the texture processing hardware subsequently accesses the surface via a second view, then the accessed data may be stale data from the cache line corresponding to the second view, rather than the updated data from the cache line corresponding to the first view. One possible solution is that the texture processing hardware may invalidate all cache lines when data is written to any cache lines. However, such an approach may substantially increase cache misses and accesses to system memory. As a result, cache performance may be reduced and power consumption may increase.
As the foregoing illustrates, what is needed in the art is an improved technique for implementing coherent cache operations in a texture cache memory.